1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a power-up signal generation circuit of a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit (IC) includes an internal power supply voltage generation unit configured to supply internal power supply voltages in response to an external power supply voltage, thereby stably operating various internal logic circuitry and other elements. If the internal power supply voltages does not have a proper voltage level during the application of the external power supply voltage, a malfunction such as latch-up, occur. In this case, it is difficult to secure the reliability of the semiconductor IC.
When the internal logic circuitry is not initialized to have a specific value before power supply voltages are supplied to operate the elements thereof, the IC may malfunction to input and output accurate data. Therefore, the IC may further include a circuit to initialize the internal logic circuitry before the operation of the other elements.
To prevent the latch up from occurring due to the instability of the internal power supply voltage and to initialize the internal logic circuitry, the semiconductor IC includes a power-up signal generation circuit configured to generate a power-up signal.
Semiconductor memory devices are being designed in such a manner as to perform a variety of operations in order to meet various market demands. For example, when a power supply voltage is supplied again, a semiconductor memory device is to stably maintain operation properties in a car navigation system (CNS).
FIG. 1 is a block diagram of a power-up signal generation circuit of a conventional semiconductor IC.
Referring to FIG. 1, the power-up signal generation circuit includes an external power supply voltage detection unit 110, an internal power supply voltage detection unit 120, and a combination unit 130. The external power supply voltage detection unit 110 is configured to detect a voltage level of an external power supply voltage VEXT and generate a first power-up signal PUPB. The internal power supply voltage detection unit 120 is configured to detect a voltage level of an internal power supply voltage VINT and generate a second power-up signal PUPBP. The combination unit 130 is configured to combine the first power-up signal PUPB and the second power-up signal PUPBP and generate a final power-up signal PWRUP.
FIG. 2 is a waveform diagram of signals for the power-up signal generation circuit of FIG. 1.
Referring to FIG. 2, power is externally supplied to increase the external power supply voltage VEXT. When the level of the external power supply voltage VEXT reaches a desired level, the external power supply voltage detection unit 110 detects the level such that the first power-up signal PUPB changes from a logic low level to a logic high level.
When the first power-up signal PUPB has changed to the logic high level, an internal power supply voltage generation unit is activated to operate in response to the first power-up signal PUPB. Accordingly, the internal power supply voltage VINT increases.
When the internal power supply voltage increases to a stable level, the internal power supply voltage detection unit 120 detects the level such that the second power-up signal PUPBP changes from the logic low level to the logic high level.
The combination unit 130 changes the final power-up signal PWRUP from the logic low level to the logic high level in response to both the first and second power-up signals PUPB and PUPBP being changed from the logic low level to the logic high level. Therefore, when the final power-up signal PWRUP has changed from the logic low level to the logic high level, the internal logic circuitry of the semiconductor IC is activated.
FIG. 3 illustrates a circuit configuration of the internal power supply voltage detection unit 120 of the conventional power-up signal generation circuit.
Referring to FIG. 3, the internal power supply detection unit 120 includes a first block configured to lower a voltage of a power-up detection node NC, a second block configured to raise a voltage of the power-up detection node NC, and a third block configured to output the second power-up signal PUPBP in response to a voltage change of the power-up detection node NC.
The first block includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a second NMOS transistor MN2. The first PMOS transistor MP1 has a source coupled to a terminal of the external power supply voltage VEXT and a drain coupled to a first node NA, and receives a ground voltage VSS through a gate thereof. The first NMOS transistor MN1 has a source coupled to a terminal of the ground voltage VSS and drain and gate coupled to the first node NA. The second NMOS transistor MN2 has a source coupled to the terminal of the ground voltage VSS, a drain coupled to the power-up detection node NC, and a gate coupled to the first node NA.
The second block includes a second PMOS transistor MP2 and a third PMOS transistor MP3. The second PMOS transistor MP2 has a source coupled to a terminal of the internal power supply voltage VINT and drain and gate coupled to a second node NB. The third PMOS transistor MP3 has a source coupled to the second node NB and a drain coupled to the power-up detection node NC, and receives a ground voltage VSS through a gate thereof.
The third block includes an inverter INV1, a fourth PMOS transistor MP4, and an inverter INV2. The inverter INV1 has an input node coupled to the power-up detection node NC. The fourth PMOS transistor MP4 has a source coupled to the terminal of the internal power supply voltage VINT, a drain coupled to the power-up detection node NC, and a gate coupled to an output node ND of the inverter INV1. The inverter INV2 has an input node coupled to the output node ND and outputs the second power-up signal PUPBP.
When the external power supply voltage VEXT is supplied in a power-up sequence, the voltage of the first node NA increases to a threshold voltage VTH of the first NMOS transistor MN1. Accordingly, the second NMOS transistor MN2 is turned on to lower the voltage level of the power-up detection node NC.
When the internal power supply voltage generation unit operates to increase the voltage level of the internal power supply voltage VINT, the second PMOS transistor MP2 is turned on to increase the voltage level of the power-up detection node NC. At this time, the power-up detection node NC is continuously discharged by the second NMOS transistor MN2. However, since the voltage level raising ability of the second PMOS transistor MP2 and the third PMOS transistor MP3 is greater than the voltage level lowering ability of the second NMOS transistor MN2, the voltage level of the power-up detection node NC increases.
As such, when the voltage level of the power-up detection node NC increases to exceed a logic threshold value of the inverter INV1, the second power-up signal PUPBP changes to the logic high level. Since the voltage of the output node ND changes to the logic low level, the fourth PMOS transistor MP4 is turned on to latch the voltage of the power-up detection node NC to the logic high level.
When a system power is reset, the external supply voltage VEXT is not supplied, and the internal power supply voltage VINT has the level of a ground voltage VSS. In this case, since the voltage of the power-up detection node NC changes from the logic high level to the logic low level, the second power-up signal PUPBP changes from the logic high level to the logic low level and the final power-up signal PWRUP changes from the logic high level to the logic low level.
When the system power is resupplied, since the first power-up signal PUPB, the second power-up signal PUPBP, and the final power-up signal PWRUP change from the logic low level to the logic high level, the internal logic circuitry of the semiconductor IC is initialized to a specific value.
However, when the system power is supplied again, residual supply voltage may exist in the system. FIG. 4 is an operation waveform diagram of the external power supply voltage having the residual supply voltage when the system power is resupplied.
When the system power is reset and the external power supply voltage VEXT is unstably discharged, the power-up detection node NC of the internal power supply voltage detection unit 120 is not completely discharged from the logic high level to the logic low level. If the voltage level of the power-up detection node NC is maintained higher than the threshold voltage level of the inverter INV1, the second power-up signal PUPBP continuously maintains the logic high level. Accordingly, since the internal logic circuitry of the semiconductor IC is not initialized even though the system power is resupplied, a malfunction may occur.
Meanwhile, the MOS transistor has a temperature characteristic such that the threshold voltage decreases with a temperature increase (−2 mV/° C.). That is, at a high temperature, the threshold voltage decreases in comparison with the threshold voltage at a normal temperature. On the other hand, at a low temperature, the threshold voltage increases in comparison with at a normal temperature. Therefore, the threshold voltage VTH of the NMOS transistor NM2 increases in a low-temperature environment. This means that discharging ability of the NMOS transistor NM2 for the power-up detection node NC decreases and the power-up detection node NC may not be completely discharged when the system power is reset.